Process-Induced Thermal Stress of Through Silicon Via and Its Releasing Structure Design

SUN Han; WANG Wei; CHEN Jing; JIN Yu-feng

doi:10.3879/j.issn.1000-0887.2014.03.008

Volume 35 Issue 3

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SUN Han, WANG Wei, CHEN Jing, JIN Yu-feng. Process-Induced Thermal Stress of Through Silicon Via and Its Releasing Structure Design[J]. Applied Mathematics and Mechanics, 2014, 35(3): 295-304. doi: 10.3879/j.issn.1000-0887.2014.03.008

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Process-Induced Thermal Stress of Through Silicon Via and Its Releasing Structure Design

doi: 10.3879/j.issn.1000-0887.2014.03.008

¹Institute of Microelectronics, Peking University, Beijing 100871, P.R.China;²Shenzhen Graduate School, Peking University, Shenzhen, Guangdong 518055, P.R.China

Funds: The National Science and Technology Major Project of China（2009ZX02038-02）

Received Date: 2013-10-06
Rev Recd Date: 2014-01-07
Publish Date: 2014-03-15

Abstract

Abstract

In the process of through silicon via (TSV) for 3D system in package (3D SiP), thermal stress changes the mobility of carriers of silicon around TSV, and then influences the whole 3D SiP chip performance. Aimed at this problem, a new stress-releasing structure was proposed, named thermal-stress-releasing groove. Stress on the silicon substrate surface outside the groove can be isolated to a low level especially for large-sized TSV applications. Numerical simulation was used to obtain the relationship between the groove structure parameters and the resulting thermal stress distribution. Parameters including depth and width of the releasing groove and distance from the groove to the pad edge were also simulated to obtain the proportion of stress reduction. The numerical results show that, 40%~60% of the previous thermal stress could be reduced, so could keep-off-zone area, through the proposed stress-releasing groove design.
- through silicon via,
- thermal-stress-releasing,
- groove structure,
- numerical simulation,
- design suggestion

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References(7)

References

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